Digital circuits in Large Scale Integration (LSI) used for processors are operated in synchronization with clock signals. Furthermore, the LSI is driven by a power supply voltage supplied from a processor power supply.
The power supply voltage supplied to the LSI sometimes varies. For example, due to an effect of power supply noise generated due to large current consumption at a transition timing of a clock, a change in voltage of the frequency band determined based on the impedance, such as a power supply wiring, the stabilization capacity, or the like, is generated in the power supply voltage.
If the power supply voltage is decreased, there may be a case in which a speed of a signal propagated in a signal path in the LSI is decreased. In the signal path in the LSI, a critical path in which propagation of a signal within a cycle of a single clock is requested is present. If a speed of the signal is decreased, in a critical path having a small timing margin of the signal propagation in the signal path in the LSI, because a delay time is increased by an amount equal to or greater than the clock cycle and a timing error is generated, an appropriate data transfer is not able to be performed.
In order to avoid such a timing error, in the LSI used for processors, or the like, there is an LSI that adaptively controls the operating frequency in accordance with a decrease in power supply voltage. Specifically, control is performed such that voltage variations are converted to delay variations, a time difference is measured with respect to the subject delay variation by using a time-to-digital converter (TDC), the oscillation cycle of a phase locked loop (PLL) circuit is increased by an amount corresponding to the subject time difference.
Furthermore, as a technology for avoiding a timing error, there is a conventional technology for matching an amount of delay of a critical path circuit with that of a clock generation circuit by using, for the clock generation circuit, a circuit having the same configuration as that of the critical path circuit in the control circuit. Furthermore, there is a conventional technology for measuring a delay time in a control circuit and controlling a clock frequency in accordance with the measurement result. Furthermore, there is a conventional technology for adjusting a power supply voltage value with respect to an unmeasured operating frequency by using a critical path monitor circuit in which a correction is added based on the power supply voltage value that is associated with the measured operating frequency acquired from a table that is used to set the operating frequency of a CPU and a power supply voltage value. Furthermore, there is a conventional technology for storing data unique to a chip that provides variations in performance of a nonvolatile memory during a production test.
Patent Document 1: Japanese Laid-open Patent Publication No. 2004-199133
Patent Document 2: Japanese Laid-open Patent Publication No. 07-253824
Patent Document 3: International Publication Pamphlet No. WO 2015/008372
Patent Document 4: Japanese National Publication of International Patent Application No. 2010-511247
However, the measurement time resolution of a TDC and the cycle modulation time resolution of a digitally controlled oscillator (DCO) in a PLL are changed in accordance with the Process Voltage Temperature (PVT) condition representing the three conditions of a process, a voltage, and a temperature. Here, the PVT condition is designed such that the measurement time resolution of the TDC is equal to the cycle modulation time resolution of the DCO is set to a reference condition. If the process is slower than the reference condition, the measurement time resolution of the TDC is greater than that obtained under the reference condition and the frequency time resolution of the DCO is smaller than that obtained under the reference condition. In contrast, if the process is faster than the reference condition, the measurement time resolution of the TDC is smaller than that obtained under the reference condition and the frequency time resolution of the DCO is greater than that obtained under the reference condition. Furthermore, if the voltage is higher than the reference condition, the measurement time resolution of the TDC is smaller than that obtained under the reference condition and the frequency time resolution of the DCO is greater than that obtained under the reference condition. In contrast, if a voltage is lower than the reference condition, the measurement time resolution of the TDC is greater than that obtained under the reference condition and the frequency time resolution of the DCO is smaller than that obtained under the reference condition. In this way, the variations in delay time given by the variations in the processes and the voltages are opposite directions regarding the measurement time resolution of the TDC and the frequency time resolution of the DCO. Consequently, a change in the PVT condition may possibly decrease the accuracy of the adaptive frequency control.
Furthermore, even when using the conventional technology for using, for the clock generation circuit, the circuit having the same configuration as that of the critical path circuit in the control circuit, a difference between the measurement time resolution of the TDC and the frequency time resolution of the DCO is increased and it is difficult to improve the accuracy of the adaptive frequency control. Furthermore, in the conventional technology for controlling the clock frequency in accordance with the measurement result of the delay time in the control circuit, the variations in the processes or the like are not considered, and it is difficult to improve the accuracy of the adaptive frequency control. Furthermore, even when using the conventional technology for adjusting the power supply voltage value by using the critical path monitor circuit in which a correction is added based on the power supply voltage value with respect to the measured operating frequency, the difference between the measurement time resolution of the TDC and the frequency time resolution of the DCO is increased and thus it is difficult to improve the accuracy of the adaptive frequency control. Furthermore, it is difficult to allow the conventional technology for storing the data unique to the chip in a nonvolatile memory to handle the adjustment of the performance of the CPU and thus it is difficult to improve the accuracy of the adaptive frequency control.